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? semiconductor components industries, llc, 2014 june, 2014 ? rev. 16 1 publication order number: mc10ep445/d mc10ep445, mc100ep445 3.3v/5v?ecl 8-bit serial/parallel converter description the mc10/100ep445 is an integrated 8?bit differential serial to parallel data converter with asynchronous data synchronization. the device has two modes of operation. cksel high mode is designed to operate nrz data rates of up to 3.3 gb/s, while cksel low mode is designed to operate at twice the internal clock data rate of up to 5.0 gb/s. the conversion sequence was chosen to convert the first serial bit to q0, the second bit to q1, etc. two selectable differential serial inputs, which are selected by sinsel, provide this device with loop?back testing capability. the mc10/100ep445 has a sync pin which, when held high for at least two consecutive clock cycles, will swallow one bit of data shifting the start of the conversion data from d n to d n+1 . each additional shift requires an additional pulse to be applied to the sync pin. control pins are provided to reset and disable internal clock circuitry. additionally, v bb pin is provided for single?ended input condition. the 100 series contains temperature compensation. features ? 1530 ps propagation delay ? 5.0 gb/s typical data rate for clksel low mode ? differential clock and serial inputs ? v bb output for single-ended input applications ? asynchronous data synchronization (sync) ? asynchronous master reset (reset) ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ?3.0 v to ?5.5 v ? open input default state ? clk enable immune to runt pulse generation ? these devices are pb?free and are rohs compliant lqfp?32 fa suffix case 873a marking diagram* *for additional marking information, refer to application note and8002/d. http://onsemi.com mcxxx ep445 awlyywwg xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week g or = pb?free package see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information 32 1 mcxx ep445 awlyyww 1 qfn32 mn suffix case 488am (note: microdot may be in either location)
mc10ep445, mc100ep445 http://onsemi.com 2 q7 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 mc10ep445 mc100ep445 q6 q5 v cc v cc q4 q3 v ee v cc sina sina v bb0 v ee sinb sinb sinsel v cc cksel v bb1 clk clk cken reset v cc q2 q1 v cc q0 pclk v cc pclk figure 1. 32?lead lqfp pinout (top view) sync warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 figure 2. 32?lead qfn pinout (top view) mc10ep445 mc100ep445 q7 q6 q5 v cc v cc q4 q3 v ee v cc sina sina v bb0 v ee sinb sinb sinsel v cc cksel v bb1 clk clk cken reset v cc q2 q1 v cc q0 pclk v cc pclk sync table 1. pin description pin sina*, sina * function ecl differential serial data input a sinsel* q0?q7 ecl parallel data outputs ecl serial input selector pin clk*, clk * ecl differential clock inputs pclk, pclk ecl differential parallel clock output sync* ecl conversion synchronizing input cksel* ecl clock input selector pin v bb0 , v bb1 output reference voltage v cc positive supply v ee negative supply sinb*, sinb * ecl differential serial data input b cken * ecl clock enable pin reset* ecl reset pin * pins will default logic low or differential logic low when left open. ep the exposed pad (ep) on the qfn?32 package bottom is thermally connected to the die for improved heat transfer out of the package. the exposed pad must be attached to a heat?sinking conduit. the pad is electrically connected to v ee . exposed pad (ep)
mc10ep445, mc100ep445 http://onsemi.com 3 table 2. truth table pin function high low sinsel select sinb input select sina input cksel q: pclk = 8:1 clk: q = 1:1 q clk q: pclk = 8:1 clk: q = 1:2 q clk cken synchronously disable internal clock circuitry synchronously enable internal clock circuitry reset asynchronous master reset synchronous enable sync asynchronously applied to swallow a data bit normal conversion process figure 3. logic diagram q0 1:2 demux 1:2 demux 1:2 demux 1:2 demux q4 q2 q6 q1 q5 q3 q7 1:2 demux 1:2 demux 1:2 demux div2 div2 pclk pclk sina sina sinb sinb sinsel t c q r cksel t c q r cken clk clk reset sync control logic v ee
mc10ep445, mc100ep445 http://onsemi.com 4 table 3. attributes characteristics value internal input pulldown resistor 75 k internal input pull?up resistor n/a esd protection human body model machine model charged device model > 2 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb?free pkg lqfp?32 qfn?32 level 2 n/a level 2 level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 993 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v ?6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ?6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w jc thermal resistance (junction?to?case) standard board 32 lqfp 12 to 17 c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm qfn?32 qfn?32 31 27 c/w c/w jc thermal resistance (junction?to?case) 2s2p qfn?32 12 c/w t sol wave solder pb?free <2 to 3 sec @ 260 c 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
mc10ep445, mc100ep445 http://onsemi.com 5 table 5. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 2) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (single?ended) 2090 2415 2155 2480 2215 2540 mv v il input low voltage (single?ended) 1365 1690 1460 1755 1490 1815 mv v bb output voltage reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mv v ihcmr input high voltage common mode range (differential configuration) (note 4) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ?2.2 v. 3. all loading with 50 to v cc ? 2.0 v. 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 6. 10ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 5) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current (note 6) 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (single?ended) 3790 4115 3855 4180 3915 4240 mv v il input low voltage (single?ended) 3065 3390 3130 3455 3190 3515 mv v bb output voltage reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mv v ihcmr input high voltage common mode range (differential configuration) (note 8) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to ?0.5 v. 6. required 500 lfpm air flow when using +5 v power supply. for (v cc ? v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc ?v ee operation at 3.3 v. 7. all loading with 50 to v cc ? 2.0 v. 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep445, mc100ep445 http://onsemi.com 6 table 7. 10ep dc characteristics, necl v cc = 0 v, v ee = ?5.5 v to ?3.0 v (note 9) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current (note 10) 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 11) ?1135 ?1010 ?885 ?1070 ?945 ?820 ?1010 ?885 ?760 mv v ol output low voltage (note 11) ?1935 ?1810 ?1685 ?1870 ?1745 ?1620 ?1810 ?1685 ?1560 mv v ih input high voltage (single?ended) ?1210 ?885 ?1145 ?820 ?1085 ?760 mv v il input low voltage (single?ended) ?1935 ?1610 ?1870 ?1545 ?1810 ?1485 mv v bb output voltage reference ?1510 ?1410 ?1310 ?1445 ?1345 ?1245 ?1385 ?1285 ?1185 mv v ihcmr input high voltage common mode range (differential configuration) (note 12) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. input and output parameters vary 1:1 with v cc . 10. required 500 lfpm air flow when using ?5 v power supply. for (v cc ? v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc ?v ee operation at 3.3 v. 11. all loading with 50 to v cc ? 2.0 v. 12. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 8. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 13) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 14) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 14) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mv v ih input high voltage (single?ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single?ended) 1305 1675 1305 1675 1305 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential configuration) (note 15) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ?2.2 v. 14. all loading with 50 to v cc ? 2.0 v. 15. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep445, mc100ep445 http://onsemi.com 7 table 9. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 16) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current (note 17) 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 18) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 18) 3005 3180 3305 3005 3180 3305 3005 3180 3305 mv v ih input high voltage (single?ended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (single?ended) 3005 3375 3005 3375 3005 3375 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v ihcmr input high voltage common mode range (differential configuration) (note 19) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to ?0.5 v. 17. required 500 lfpm air flow when using +5 v power supply. for (v cc ? v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc ?v ee operation at 3.3 v. 18. all loading with 50 to v cc ? 2.0 v. 19. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 10. 100ep dc characteristics, necl v cc = 0 v, v ee = ?5.5 v to ?3.0 v (note 20) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current (note 21) 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 22) ?1145 ?1020 ?895 ?1145 ?1020 ?895 ?1145 ?1020 ?895 mv v ol output low voltage (note 22) ?1995 ?1820 ?1695 ?1995 ?1820 ?1695 ?1995 ?1820 ?1695 mv v ih input high voltage (single?ended) ?1225 ?880 ?1225 ?880 ?1225 ?880 mv v il input low voltage (single?ended) ?1995 ?1625 ?1995 ?1625 ?1995 ?1625 mv v bb output voltage reference ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 23) v ee + 2.0 0.0 v ee + 2.0 0.0 v ee + 2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. input and output parameters vary 1:1 with v cc . 21. required 500 lfpm air flow when using ?5.0 v power supply. for (v cc ? v ee ) > 3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc ? v ee operation at 3.3 v. 22. all loading with 50 to v cc ? 2.0 v. 23. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep445, mc100ep445 http://onsemi.com 8 table 11. ac characteristics v cc = 0 v; v ee = ?3.0 v to ?5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 24) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max f max maximum input clk frequency cksel = low (see figure 13. f max /jitter) cksel = high 2.0 2.8 2.5 3.3 2.0 2.8 2.5 3.3 1.7 2.8 2.2 3.3 ghz t plh , t phl propagation delay to clk to q output differential clk to pclk 1280 1000 1475 1240 1710 1490 1335 1050 1557 1310 1795 1580 1450 1140 1663 1420 1950 1710 ps ts setup time sina, b+ to clk+ (figure 5) cken+ to clk? (figure 6) ?400 100 ?459 50 ?420 100 ?479 50 ?440 100 ?492 50 ps t h hold time clk+ to sina, b? (figure 5) clk? to cken (figure 6) 533 45 474 ?35 550 45 490 ?35 560 45 508 ?35 ps t rr /t rr2 reset recovery (figure 4) 350 180 350 180 350 180 ps t pw minimum pulse width reset 400 400 400 ps t jitter rms random clock jitter @ 2.0 ghz clk_sel low @ 2.5 ghz clk_self high @ 3.0 ghz clk_sel high 1.5 1.0 1.5 1.5 1.0 2.0 1.5 1.5 2.5 ps v pp input voltage swing (differential configuration) (note 25) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times q/q (20% ? 80%) pclk/pclk 100 100 180 180 400 250 100 100 200 200 400 300 125 125 230 230 425 325 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 24. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. 25. v pp (min) is the minimum input swing for which ac parameters are guaranteed.
mc10ep445, mc100ep445 http://onsemi.com 9 figure 4. reset recovery reset clk t rr clk figure 5. data setup and hold time data setup time clk figure 6. cken setup and hold time cken setup time t h t s data hold time ? ? + + clk t h t s cken hold time ? ? + +
mc10ep445, mc100ep445 http://onsemi.com 10 application information the mc10/100ep445 is an integrated 1:8 serial to parallel converter with two modes of operation selected by cksel (pin 7). cksel high mode only latches data on the rising edge of the input clk and cksel low mode latches data on both the rising and falling edge of the input clk. cksel low is the open default state. either of the two differential input serial data path provided for this device, sina and sinb, can be chosen with the sinsel pin (pin 25). sina is the default input path when sinsel pin is left floating. because of internal pull?downs on the input pins, all input pins will default to logic low when left open. the two selectable serial data paths can be used for loop?back testing as well as the bit error testing. upon power?up, the internal flip?flops will attain a random state. to synchronize multiple flip?flops in the device, the reset (pin 1) must be asserted. the reset pin will disable the internal clock signal irrespective of the cken state (cken disables the internal clock circuitry). the device will grab the first stream of data after the falling edge of reset , followed by the falling edge of clk , on second rising edge of clk in either cksel modes. (see figure 6) clk reset pclk reset (asynchronous reset) reset (synchronous enable) figure 7. reset timing diagram
mc10ep445, mc100ep445 http://onsemi.com 11 for cksel low operation, the data is latched on both the rising edge and the falling edge of the clock and the time from when the serial data is latched to when the data is seen on the parallel output is 6 clock cycles (see figure 8). figure 8. timing diagram a. 1:8 serial to parallel conversion with cksel low clk sina reset cksel pclk q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 q1 q2 q3 q4 q5 q6 q7 d0 d8 d16 d1 d9 d17 d2 d10 d18 d3 d11 d19 d4 d12 d20 d5 d13 d21 d6 d14 d22 d7 d15 d23 cken 123456 number of clock cycles from data latch to q
mc10ep445, mc100ep445 http://onsemi.com 12 similarly, for cksel high operation, the data is latched only on the rising edge of the clock and the time from when the serial data is latched to when the data is seen on the parallel output is 12 clock cycles (see figure 9). figure 9. timing diagram a. 1:8 serial to parallel conversion with cksel high clk sina reset cksel pclk q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 cken 123456 number of clock cycles from data latch to q 7 8 9 10 11 12
mc10ep445, mc100ep445 http://onsemi.com 13 to allow the user to synchronize the output byte data correctly, the start bit for conversion can be moved using the sync input pin (pin 2). asynchronously asserting the sync pin will force the internal clock to swallow a clock pulse, ef fectively shifting a bit from the q n to the q n?1 output as shown in figure 10 and figure 11. for cksel low, a single pulse applied asynchronously for two consecutive clock cycles shifts the start bit for conversion from q n to q n?1 . the bit is swallowed following the two clock cycle pulse width of sync on the next triggering edge of clock (either on the rising or the falling edge of the clock). each additional shift requires an additional pulse to be applied to the sync pin. (see figure 10) figure 10. timing diagram a. 1:8 serial to parallel conversion with sync pulse at cksel low clk sina cksel pclk sync q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 q1 q2 q3 q4 q5 q6 q7 d0 d9 d17 d1 d10 d18 d2 d11 d19 d3 d12 d20 d4 d13 d21 d5 d14 d22 d6 d15 d23 d7 d16 d24 12 2 clock cycles for sync next triggering edge of clock bit d8 is swallowed
mc10ep445, mc100ep445 http://onsemi.com 14 for cksel high, a single pulse applied asynchronously for three consecutive clock cycles shifts the start bit for conversion from q n to q n?1 . the bit is swallowed following the three clock cycle pulse width of sync on the next triggering edge of clock (on the rising edge of the clock only). each additional shift requires an additional pulse to be applied to the sync pin. (see figure 11) figure 11. timing diagram a. 1:8 serial to parallel conversion with sync pulse at cksel high 12 3 clock cycles for sync next triggering edge of clock bit d8 is swallowed clk sina pclk q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 sync 3 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24
mc10ep445, mc100ep445 http://onsemi.com 15 the synchronous cken (pin 3) applied with at least one clock cycle pulse length will disable the internal clock signal. the synchronous cken will suspend all of the device activities and prevent runt pulses from being generated. the rising edge of cken followed by the falling edge of clk will suspend all activities. the first data bit will clock on the rising edge, since the falling edge of cken followed by the falling edge of the incoming clock triggers the enabling of the internal process. (see figure 12) clk pclk internal clock disabled internal clock enabled figure 12. timing diagram with cken with cksel high cksel cken the differential pclk output (pins 22 and 23) is a word framer and can help the user to synchronize the parallel data outputs. during cksel low operation, the pclk will provide a divide by 4?clock frequency, which frames the serial data in period of pclk output. likewise during cksel high operation, the pclk will provide a divide by 8?clock frequency. the v bb pin, an internally generated voltage supply, is available to this device only. for single?ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor, which will limit the current sourcing or sinking to 0.5ma. when not used, v bb should be left open. also, both outputs of the dif ferential pair must be terminated (50 to v tt = v cc ? 2 v) even if only one output is used.
mc10ep445, mc100ep445 http://onsemi.com 16 0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 figure 13. f max /jitter input clk frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) figure 14. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v
mc10ep445, mc100ep445 http://onsemi.com 17 ordering information device package shipping ? mc10ep445fag lqfp?32 (pb?free) 250 units / tray mc10ep445far2g 2000 / tape & reel mc10ep445mng qfn?32 (pb?free) 74 units / rail mc10ep445mnr4g 1000 / tape & reel MC100EP445FAG lqfp?32 (pb?free) 250 units / tray mc100ep445far2g 2000 / tape & reel mc100ep445mng qfn?32 (pb?free) 74 units / rail mc100ep445mnr4g 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc10ep445, mc100ep445 http://onsemi.com 18 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ?t? ?z? ?u? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t-u m 0.20 (0.008) z ac 32 lead lqfp case 873a?02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
mc10ep445, mc100ep445 http://onsemi.com 19 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc10ep445/d eclinps is a trademark of semiconductor components industries, llc (scillc) literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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